With the continuous development of integrated circuit (IC) technologies, the development trend for electronic products is moving towards more miniaturized and intelligent structures with high performance and high reliability. IC packaging not only has a direct impact on the performance of the integrated circuits, electronic modules, and even the systems, but also restricts the miniaturization, low-cost, and reliability of electronic systems. As the IC chip size keeps decreasing and the integration degree keeps increasing, higher and higher requirements for IC packaging technology are raised by the electronics industry.
Chinese patent publication number CN1747156C discloses a circuit integration wafer. The disclosed circuit integration wafer includes: a substrate having a surface; a ball pad located on the substrate surface; a solder mask layer formed on the surface of the substrate, with at least one opening to expose the ball pad; and a patterned metal reinforcing layer formed on the ball pad along the sidewall of the solder mask layer opening. However, when such circuit integration wafer is used, the system-level packaging integration degree may be still undesired.
On the other hand, with the trend for light, thin, short, and small products as well as increasingly high demand for system-level functionalities, the integration degree of system-level packaging needs to be further improved. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.